INSTRUCTIONS AND INSTRUCTION CODES
Computer instructions are the basic components of a machine language program. They are also known as macrooperations, since each one is comprised of a sequences of microoperations.
Each instruction initiates a sequence of microoperations that fetch operands from registers or memory, possibly perform arithmetic, logic, or shift operations, and store results in registers or memory.
Instructions are encoded as binary instruction codes. Each instruction code contains of a operation code, or opcode, which designates the overall purpose of the instruction (e.g. add, subtract, move, input, etc.). The number of bits allocated for the opcode determined how many different instructions the architecture supports.
In addition to the opcode, many instructions also contain one or more operands, which indicate where in registers or memory the data required for the operation is located. For example, and add instruction requires two operands, and a not instruction requires one.
The basic computer has three instruction code formats. The Operation code (opcode) part of the instruction contains 3 bits and remaining 13 bits depends upon the operation code encountered.
The operation code of an instruction is a group of bits that define operations such as add, subtract, multiply, shift and compliment. The number of bits required for the operation code depends upon the total number of operations available on the computer. The operation code must consist of at least n bits for a given 2^n operations. The operation part of an instruction code specifies the operation to be performed.
There are three types of formats:
- Memory Reference Instruction
It uses 12 bits to specify the address and 1 bit to specify the addressing mode (I). I is equal to 0 for direct address and 1 for indirect address.
2. Register Reference Instruction
These instructions are recognized by the opcode 111 with a 0 in the left most bit of instruction. The other 12 bits specify the operation to be executed.
3. Input-Output Instruction
These instructions are recognized by the operation code 111 with a 1 in the left most bit of instruction. The remaining 12 bits are used to specify the input-output operation.
Format of Instruction
The format of an instruction is depicted in a rectangular box symbolizing the bits of an instruction. Basic fields of an instruction format are given below:
- An operation code field that specifies the operation to be performed.
- An address field that designates the memory address or register.
- A mode field that specifies the way the operand of effective address is determined.
Computers may have instructions of different lengths containing varying number of addresses. The number of address field in the instruction format depends upon the internal organization of its registers.
Timing and Control
All sequential circuits in the Basic Computer CPU are driven by a master clock, with the exception of the INPR register.
At each clock pulse, the control unit sends control signals to control inputs of the bus, the registers, and the ALU.
Control unit design and implementation can be done by two general methods:
- A hardwired control unit is designed from scratch using traditional digital logic design techniques to produce a minimal, optimized circuit. In other words, the control unit is like an ASIC (application-specific integrated circuit).
- A microprogrammed control unit is built from some sort of ROM. The desired control signals are simply stored in the ROM, and retrieved in sequence to drive the microoperations needed by a particular instruction.
we use primarily the timing signals and bits from the instruction register to construct control functions. These are the independent variables in the CPU. Control inputs on CPU components, such as ACload, S0, etc. are dependent variables, i.e. functions of the timing signals and IR bits.
The following components provide most of the independent variables for the Boolean functions driving control inputs such as ACLD, PCINR, etc.
- I flip-flop
- Opcode field from the instruction code
- Address bits from the instruction code
- 4-bit counter with INR, CLR (CLR=1 at power-on)
The sequence counter along with the decoder on its outputs generate a regular sequence of timing signals that we will refer to as T0, T1, etc.
The CPU performs a sequence of microoperations for each instruction. The sequence for each instruction of the Basic Computer can be refined into 4 abstract phases:
- Fetch instruction
- Fetch operand
Instruction Fetch and Decode
The instruction fetch and decode phases are the same for all instructions, so the control functions and microoperations will be independent of the instruction code.
Everything that happens in this phase is driven entirely by timing variables T0, T1 and T2. Hence, all control inputs in the CPU during fetch and decode are functions of these three variables alone.
T0: AR ← PC
T1: IR ← M[AR], PC ← PC + 1
T2: D0-7 ← decoded IR(12-14), AR ← IR(0-11), I ← IR(15)
For every timing cycle, we assume SC ← SC + 1 unless it is stated that SC ← 0.
Program execution begins with:
PC ← address of first instruction, SC ← 0
After this, the SC is incremented at each clock cycle until an instruction is completed, and then it is cleared to begin the next instruction. This process repeats until a HLT instruction is executed, or until the power is shut off.
Note that incrementing the PC at time T1 assumes that the next instruction is at the next address. This may not be the case if the current instruction is a branch instruction. However, performing the increment here will save time if the next instruction immediately follows, and will do no harm if it doesn’t. The incremented PC value is simply overwritten by branch instructions.
By time T2, the opcode has been decoded by the decoder attached to IR(12-14), and the control signals D0-7 are available. At pulse T2, IR(15) is loaded into the I flip-flop. Hence, all of these signals are available for use at pulse T3.
Determining the Instruction Type
D7 indicates that the opcode field is 111, and this is either a register or I/O instruction. (i.e. it is not a memory-reference instruction.)
The I bit allows us to distinguish between register and I/O instructions.
D7′ indicates a memory-reference instruction. In this case, the I bit determines the addressing mode. What happens at time T3 therefore depends on the two variables D7 and I.
D7I’T3: Execute register-reference instruction.
D7IT3: Execute I/O instruction.
- Memory-reference with indirect addressing:
D7’IT3: AR ← M[AR]
- Memory-reference with direct addressing:
D7’I’T3: Nothing. Effective address is already in AR. This wastes a clock cycle when direct addressing is used, but it simplifies the memory-reference execute phase by ensuring tha the CPU is in a known state at time T4.
Register-reference Execute Phase
The control function D7I’ indicates a register-reference instruction, but which one?
Regardless of which instruction it is, T3 will be the last timing cycle for this instruction, and we will want the next clock pulse to start the timing cycle over at T0 and fetch the next instruction.
Since D7I’T3 is common to all register-reference instructions, we will abbreviate it as simple ‘r’.
D7I’T3: SC ← 0
r: SC ← 0
What is the Boolean function for SCCLR?
The CLA instruction is indicated by instruction code 780016 (0 111 1000000000002).
The leftmost 4 bits indicate only that this is a register-reference instruction. The rightmost 12 bits indicate that it is the CLA instruction.
How many register-reference instructions are possible with 12 bits to represent the opcode?
The Basic Computer does not encode the bits for register-reference instructions as a binary number, but instead uses them directly. Hence, only one of these bits can be 1 for a given instruction, and we are limited to 12 register-reference instructions.
For the register-reference execute phase, all control inputs in the CPU are functions of T3, r and one of the variables B0 through B11, which come directly from IR(0-11).
CMA 00100000 …
Since B11 indicates a CLA instruction the execute cycle for CLA is driven by the function rB11.
rB11: AC ← 0
ACCLR = ?
The “skip” instructions, SPA, SNA, SZA, and SZE are primitive branch instructions that simply skip the next instruction if the condition is met. For example, SPA (skip on positive accumulator) performs the following:
if ( AC >= 0 ) then PC ← PC + 1
A processor register (CPU register) is one of a small set of data holding places that are part of the computer processor. A register may hold an instruction, a storage address, or any kind of data (such as a bit sequence or individual characters). Some instructions specify registers as part of the instruction.
Types of register
- PC/IP (Program Counter / Instruction Pointer, 12 bits) holds memory address of current/next instruction to be executed. Updated as part of the instruction cycle. (Usually incremented, but may be parallel loaded by jump/branch instructions.
- IR (Instruction Register, 16 bits) holds the instruction code of the instruction currently executing. Outputs of this register are hardwired to specific logic in the control unit, which interprets the bits to generate control signals.
- AR (Address Register, 12 bits) is used to interface with the memory unit. All memory-references are initiated by loading the memory address into AR.
- AC (Accumulator, 16 bits) is used for all mathematical, logic, and shift operations operations except incrementing and clearing other registers (most have built-in increment and clear capability). It is the destination for all ALU operations, and a source for all dyadic (two-operand) operations.
- DR (Data Register, 16 bits) is used to contain a second operand for dyadic operations such as add, sub, and, or.
- TR (Temporary Register, 16 bits) is an extra register for storing data or addresses.
- INPR and OUTR (Input and Output Registers, 8 bits) are used to communicate with the input and output devices. (The Basic Computer has one input device and one output device.)
General purpose register
General purpose registers are used to store temporary data within the microprocessor. There are 8 general purpose registers in 8086 microprocessor. AX – This is the accumulator. It is of 16 bits and is divided into two 8-bit registers AH and AL to also perform 8-bit instructions.
Accumulator, is a register to perform calculation as well as holding the results of computations. Basic operations like add, subtract, multiplication or division can occur within the accumulator register. Accumulator register stores the operands used in arithmetic operations and hold the results of calculations formed. T. C. Bartee and D. J. Chapman (1965) commented that when two numbers are added, the augend is initially stored in the accumulator register; the addend is then read from the memory; and the sum is placed in the accumulator. Arithmetic operations such as division and multiplication are performed similar as the process above. Furthermore, the accumulator can be used to perform the logical functions like AND and OR.
As indicated by Irv.E (2010), the memory data register (MDR), sometimes known as the memory buffer register, will hold a data value that is being stored to or retrieved from the memory location currently addressed by the memory address register. Memory data register and memory address register (to be discussed later) are more closely associated with the workings of memory.
Specail purpose register
Some registers serve specific functions within the CPU. Several of the more important of these registers are instruction register and program counter.
In CPU, instruction register is used to store or hold the actual instruction being loaded, decoded or executed currently. After loaded the instruction from memory, it is decoded and then executed.
Consequently, instruction register serves the data input to the part of decoding process. According to Stephen D. (1994), decoding refers to the separation of the instruction into its op code and operands, the movement of data (such as loading data into a register from a memory address in one of the operands), and the generation of control signals to the ALU for instruction execution.
Another special-purpose register in CPU is program counter, also called the instruction pointer, holds the address of the instruction being executed currently or the address of the following instruction to be executed. For example, suppose there is an instruction being executed and after the arithmetic and logic unit (ALU) processed it, the processor will search for the second instruction to be executed. Thus, program counter is responsible for the following process, which is to track and store the address of the following instruction that is going to be executed for the purpose of saving time.
Input output interrupts
An interrupt that is caused by (a) the completion of an input-output operation or (b) operator intervention at the input-output unit.
Since input and output devices are not under the full control of the CPU (I/O events are asynchronous), the CPU must somehow be told when an input device has new input ready to send, and an output device is ready to receive more output.
The FGI flip-flop is set to 1 after a new character is shifted into INPR. This is done by the I/O interface, not by the control unit. This is an example of an asynchronous input event (not synchronized with or controlled by the CPU).
The FGI flip-flop must be cleared after transferring the INPR to AC. This must be done as a microoperation controlled by the CU, so we must include it in the CU design.
The FGO flip-flop is set to 1 by the I/O interface after the terminal has finished displaying the last character sent. It must be cleared by the CPU after transferring a character into OUTR.
Since the keyboard controller only sets FGI and the CPU only clears it, a JK flip-flop is convenient:
Keyboard controller —>| J Q |—–>
| | |
+——–\—–\ | |
) or >—–>|> FGI |
+——–/—–/ | |
| | |
CPU——————–>| K |
There are two common methods for detecting when I/O devices are ready, namely software polling and interrupts. These two methods are discussed in the following sections.
In software polling, the software is responsible for checking the status of I/O devices and initiating transactions when the device is ready. The simplest form of software polling is called spin waiting. A spin waiting loop does nothing but watch the status of a device until it becomes ready. When it is ready, the loop exits and the I/O transaction is performed.
With interrupts, the running program is not responsible for checking the status of I/O devices. Instead, it simply does its own work, and assumes that I/O will take care of itself!
When a device becomes ready, the CPU hardware initiates a branch to an I/O subprogram called an interrupt service routine (ISR), which handles the I/O transaction with the device.
An interrupt can occur during any instruction cycle as long as interrupts are enabled. When the current instruction completes, the CPU interrupts the flow of the program, executes the ISR, and then resumes the program. The program itself is not involved and is in fact unaware that it has been interrupted.
Cache Memory is a special very high-speed memory. It is used to speed up and synchronizing with high-speed CPU. Cache memory is costlier than main memory or disk memory but economical than CPU registers. Cache memory is an extremely fast memory type that acts as a buffer between RAM and the CPU. It holds frequently requested data and instructions so that they are immediately available to the CPU when needed.
Cache memory is used to reduce the average time to access data from the Main memory. The cache is a smaller and faster memory which stores copies of the data from frequently used main memory locations.